1. Field of the Invention
The present invention relates to a spread spectrum demodulation circuit and spread spectrum communication apparatus for demodulating a transmission information signal from a reception signal to which a quadrature phase shift keying and a spread spectrum modulation are performed.
Further, the present invention relates to a delay-detection-type demodulation circuit and delay-detection-type communication apparatus for demodulating a transmission information signal from a reception signal to which a quadrature phase shift keying is performed.
2. Description of the Related Art
A spread spectrum communication scheme (SS communication scheme) has recently been paid attention as a private communication system, because of high resistance to noises and excellency of security and secrecy. In the SS communication scheme, a carrier wave which is phase-modulated by information to be transmitted (transmission information) is spread-spectrum-modulated (SS modulated) by a predetermined code sequence having a predetermined high chip rate, to thereby obtain a spread spectrum signal (SS signal) used as a transmission signal. The code sequence includes a pseudo noise code sequence (PN code sequence) or a Barker code sequence, and the SS modulation scheme includes a direct spread scheme (DS scheme) and a frequency hopping scheme (FH scheme).
In the SS communication system, it is necessary for a receiver to have a demodulator for demodulating the transmitted SS signal. For example, if the carrier wave is SS-modulated through the DS scheme using the PN code sequence, the receiver demodulates it by using the same PN code sequence as that used by the transmitter. A demodulator to be used for such a purpose is broadly classified into a demodulator using an IC and a demodulator using a surface acoustic wave element. The surface acoustic wave element to be used for the demodulator can be realized cost effectively and in simple structure by utilizing photolithography, and so the demodulator of this type is being paid attention.
The surface acoustic wave element is classified from its configuration into a surface acoustic wave matched filer and a surface acoustic wave convolver. Since the surface acoustic wave convolver can select the PN code sequence for demodulation, it is particularly suitable for the field where security and secrecy are required. Since the surface acoustic wave matched filter uses a fixed code sequence for demodulation, a peripheral circuit can be simplified correspondingly and the whole system can be made inexpensive. Therefore, the surface acoustic wave matched filter is being paid attention for use with a demodulator for a small SS communication system such as an intra-radio LAN. Various types of surface acoustic wave matched filters and demodulators using such matched filters have been proposed.
A conventional demodulation circuit using a surface acoustic wave matched filter compatible with a quadrature phase shift keying scheme (QPSK scheme) is shown in a block diagram of FIG. 10. FIG. 10 illustrates a conventional spread spectrum demodulation circuit (SS demodulation circuit). The demodulation circuit comprises a correlation signal generator 51, a first delay element 52a, a first adder 53a for adding a correlation signal output from the correlation signal generator 51 and an output signal (first delay signal) of the first delay element 52a, signal lines 54a and 55a, and a first reproduction circuit 56a for reproducing data from an output signal (first addition signal) of the first adder 53a. For signal inputs to the first adder 53a, the delay amount of the first delay element 52a is set so that the input signal (first delay signal) from the first delay element 52a is delayed from the input signal (correlation signal) from the correlation signal generator 51 by T+(.+-.n+5.times.a/8)/fc, where T represents one period of a reception signal to be demodulated, n represents an integer from "0" to a value equal to or smaller than a ratio multiplied by "2" of the carrier frequency fc of a signal input to a means for retrieving correlation signal to a chip rate, and 1/2.ltoreq.a.ltoreq.3/2.
The demodulation circuit further comprises a second delay element 52b, a second adder 53b for adding the correlation signal output from the correlation signal generator 51 and an output signal (second delay signal) of the second delay element 52b, signal lines 54b and 55b, a second reproduction circuit 56b for reproducing data from an output signal (second addition signal) of the second adder 53b, and a synthesizing circuit 57 for synthesizing output data of the first reproduction circuit 56a and output data of the second reproduction circuits 56b. A data demodulation circuit 58 is constituted of the first and second reproduction circuits 56a and 56b and the synthesizing circuit 57. For signal inputs to the second adder 53b, the delay amount of the second delay element 52b is set so that the input signal (second delay signal) from the second delay element 52b is delayed from the input signal (correlation signal) from the correlation signal generator 51 by T+(.+-.m-5.times.a/8)/fc, where m represents an integer from "0" to a value equal to or smaller than a ratio multiplied by "2" of a carrier frequency fc of a signal input to a means for retrieving correlation signal to a chip rate. It is preferable that n=0, m=0, and a=1.
FIG. 11 is a phase transition diagram showing the phase states of the surface acoustic wave matched filer and delay elements during demodulation of a signal compatible with the QPSK scheme. In FIG. 11, (A, B, C, D) indicates four phase states, i.e. A(10), B(00), C(01) and D(11), corresponding to the QPSK scheme in the output signal of the surface acoustic wave matched filter. Assuming that a=1, (A', B', C', D') indicates the phase states of the signal delayed in the first delay element 52a by T+(.+-.n+5/8)/fc, and (A", B", C", D") indicates the phase states of the signal delayed in the second delay element 52b by T+(.+-.m-5/8)/fc. For example, when the signal in the state A is delayed in the first delay element 52a by T+(.+-.n+5/8)/fc, the state A transits to the state A'. When the signal in the state A is delayed in the second delay element 52b by T+(.+-.m-5/8)/fc, the state A transits to the state A".
In FIG. 12, (a) illustrates a timing of the information signal to be transmitted (transmission information signal) D21; (b) illustrates a timing of a signal D22 which is obtained by subjecting the differential coding (to be later described) to the transmission information signal D21; (c) illustrates a timing of a correlation signal S21 output from the correlation signal generator 51; (d) illustrates a timing of a first delay signal S22 delayed in the first delay element 52a by T+(.+-.n+5/8)/fc; (e) illustrates a timing of a first addition signal S23 obtained by adding the correlation signal S21 and the first delay signal S22; (f) illustrates a timing of data D23 reproduced from the first addition signal S23 in the first reproduction circuit 56a; (g) illustrates a timing of a second delay signal S24 delayed in the second delay element 52b by T+(.+-.m-5/8)/fc; (h) illustrates a timing of a second addition signal S25 obtained by adding the correlation signal S21 and the second delay signal S24; (i) illustrates a timing of data D24 reproduced from the second addition signal S25 in the second reproduction circuit 56b; (j) illustrates a timing of an information signal D25 obtained by synthesizing in the synthesizing circuit 57 the data D23 reproduced in the first reproduction circuit 56a and the data D24 reproduced in the second reproduction circuit 56b; and (k) illustrates a timing of an actual signal waveform S26. That is, in (c) to (e), (g) and (h) of FIG. 12, only envelopes are shown for simplifying, but the actual signal waveform is similar to the signal waveform S26.
Next, the operation of the SS demodulation circuit shown in FIG. 10 will be described with reference to FIGS. 11 and 12. In the following, it is assumed that the differential coding of the transmission information signal D21 is performed in the transmitter. When the differential coding (DD2(i)=DD1(i)+DD2(i-1)) is subjected to the transmission information signal D21 (10000111011110: repetitive data of phase information ABCDCDA), the transmission information signal D21 is changed to a signal D22 (10100011100100: AABDACB) (see (a) and (b) in FIG. 12). Therefore, in the SS demodulator unit, the output signal (correlation signal) of the correlation signal generator 51 has an output waveform S21 with the phase information corresponding to the differential-coded information (see (c) in FIG. 12). When the correlation signal S21 and the output signal (first delay signal) S22 having the phase information (B'A'A'B'D'A'C') delayed by T+(.+-.n+5/8)/fc in the first delay element 52a (see (d) in FIG. 12) are added in the first adder 53a, the output waveform S23 is obtained (see (e) in FIG. 12). Because a large addition waveform is obtained when the output signal having the phase information A is added to an output waveform having the phase difference of .+-.45 degrees such as B' or C', whereas a small addition waveform is obtained when the output signal having the phase information A is added to an output waveform having the phase difference of .+-.225 degrees such as A' or D'. When the correlation signal S21 and the output signal (second delay signal) S24 having the phase information (B"A"A"B"D"A"C") delayed by T+(.+-.m-5/8)/fc in the second delay element 52b (see (g) in FIG. 12) are added in the second adder 53b, the output waveform S25 is obtained (see (h) in FIG. 12). Because a large addition waveform is obtained when the output signal having the phase information A is added to the output waveform having the phase difference of .+-.45 degrees such as C" or D", whereas a small addition waveform is obtained when the output signal having the phase information A is added to the output waveform having the phase difference of .+-.225 degrees such as A" or B". Clocks are generated from the waveforms of the first and second addition signals S23 and S25. The data D23 (see (f) in FIG. 12) is reproduced by setting the output waveform S23 having the large level to "1" and that having the small level to "0" in the first reproduction circuit 56a. Further, the data D24 (see (i) in FIG. 12) is reproduced by setting the output waveform S25 having the large level to "1" and that having the small level to "0" in the second reproduction circuit 56b. Then, the data D23 and the data D24 are synthesized in the synthesizing circuit 57 to obtain the demodulated data D25 (10000111011110) (see (j) in FIG. 12). As a result, the signal compatible with the QPSK scheme can be demodulated to recover the original data D21. That is, the difference of delay amount between the first and second delay elements 52a and 52b is (T+(.+-.n+5/8)/fc);-(T+(.+-.m-5/8)/fc)=(.+-.(n+m)+1)/fc+(1/4)/fc, and therefore the demodulation for the QPSK scheme can be performed. Because the first term of the right side is 2.pi. in terms of phase, so that the phase difference becomes 90 degrees only under consideration of the second term.
As mentioned above, the SS signal of the QPSK scheme can be demodulated by using the simple configuration which includes the surface acoustic wave matched filer, the delay elements 52a and 52b having different delay amounts, the adders 53a and 53b, and the data demodulation circuit 58.
However, the ratio between levels "1" and "0" of the addition signal from the adder is theoretically about 2.413. Therefore, in the conventional SS demodulator, if noises become large and the S/N ratio becomes low, the data reproduction cannot be performed correctly and the error rate increases.